1. Field of the Invention
The present invention relates to a data processing apparatus including a plurality of circuit units operating with different clock cycles. More particularly, it relates to a technique of efficiently carrying out a data transfer between each circuit unit.
In a data processing apparatus having a plurality of circuit units operating with different clock cycles, each circuit unit carries out a processing of monitoring respective operations of other circuit units. In this case, it is necessary to establish a system by which it is possible to realize an effective and precise processing of monitoring.
2. Description of the Related Art
For example, in a data processing apparatus including a first circuit unit operating with clocks of a first predetermined cycle and a second circuit unit operating with clocks of a second predetermined cycle different from the first clock cycle, where a data transfer is carried out from the first circuit unit to the second circuit unit, the second circuit unit needs to have a function of judging whether or not the data transfer processing has been normally carried out.
Such a function is generally realized by providing a timer in the second circuit unit which is a receiver of data, by counting a lapse of time from the start of the data transfer by means of the timer, and by judging whether or not the data transfer is completed within a predetermined lapse of time.
Such a counting processing is needed for monitoring the time required for the data transfer. Thus it should be essentially carried out by counting the number of clocks in the first circuit unit which is a transmitter of data. In the prior art, however, a timer for the counting processing has been provided in the second circuit unit which is a receiver of data, and the counting processing has been carried out by counting the number of clocks in the second circuit unit.
Namely, the prior art has adopted a method of taking into consideration the clock cycle used in the first circuit unit which is a transmitter of data, and the clock cycle used in the second circuit unit which is a receiver of data, then setting the number of clocks in the second circuit unit corresponding to the normal data transfer time, and using the set number of clocks as a reference value to thereby estimate the data transfer time.
According to the above prior art, however, where the ratio of the clock cycle in the first circuit unit to that in the second circuit unit is changed to one different from the initially expected (for example, where the clock cycle in the first circuit unit is reduced for a high speed operation in a change of design at a later stage), a problem occurs in that it is impossible to realize an accurate monitoring processing. Namely, a drawback arises in that time is over in a shorter time than the normal data transfer time initially expected, and thus it is impossible to realize an accurate monitoring processing.
To cope with the problem, another prior art has adopted a method of setting the number of clocks in the second circuit unit corresponding to the normal data transfer time, with an ample time margin. According to the method, however, a problem occurs in that, since a counting processing is carried out uselessly by time corresponding to the time margin, it is impossible to efficiently carry out the data transfer processing.